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d a t a sh eet product speci?cation file under integrated circuits, ic12 2002 jan 17 integrated circuits om6211 48 84 dot matrix lcd driver
2002 jan 17 2 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 contents 1 features 2 applications 3 general description 4 ordering information 5 block diagram 6 pinning 7 pin functions 7.1 row 0 to row 47 row driver outputs 7.2 col 0 to col 83 column driver outputs 7.3 v ss1 and v ss2 : negative power supply rails 7.4 v dd1 to v dd3 : positive power supply rails 7.5 v lcdout , v lcdin and v lcdsense : lcd power supply 7.6 v os4 to v os0 : calibration inputs 7.7 sdin: serial data input 7.8 sdout: serial data output 7.9 sclk: serial clock input 7.10 sce: chip enable 7.11 osc: oscillator 7.12 mx: horizontal mirroring 7.13 id3 and id4: identification inputs 7.14 res: reset 7.15 t1, t2, t3, t4, t5 and t6: test pins 8 block diagram functions 8.1 oscillator 8.2 serial interface control 8.3 command decoder 8.4 display data ram (ddram) 8.5 timing generator 8.6 address counter (ac) 8.7 display address counter 8.8 v lcd generator 8.9 bias voltage generator 8.10 lcd row and column drivers 8.11 reset 9 functional description 9.1 reset 9.2 power-down 9.3 lcd voltage selector 9.4 oscillator 9.5 timing 9.6 column driver outputs 9.7 row driver outputs 9.8 drive waveforms 9.9 bias system 9.10 voltage multiplier control 9.11 temperature compensation 9.12 v lcd generator 10 initialization 10.1 initialization sequence 10.2 frame frequency calibration (oc) 11 addressing 11.1 addressing 11.2 serial interface 11.2.1 write mode 11.2.2 read mode 12 instructions 12.1 instruction set 13 limiting values 14 handling 15 dc characteristics 16 ac characteristics 16.1 serial interface timing 16.2 reset timing 17 application information 18 module maker programming 18.1 v lcd calibration 18.2 v pr default value 18.3 seal bit 18.4 otp architecture 18.5 serial interface commands 18.5.1 enable otp 18.5.2 calmm 18.5.3 load factory default 18.5.4 refresh 18.6 example of filling the shift register 18.7 programming flow 18.8 programming specification 19 bonding pad locations 20 device protection diagram 21 tray information 22 data sheet status 23 definitions 24 disclaimers
2002 jan 17 3 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 1 features single-chip lcd controller/driver 48 row, 84 column outputs display data ram 48 84 bits 3-line serial interface, maximum 4.0 mbit/s on-chip: C generation of lcd supply voltage v lcd C generation of intermediate lcd bias voltages C oscillator (requires no external components). cmos compatible inputs mux rat e1:48 logic supply voltage range v dd1 to v ss : C 1.7 to 2.3 v. supply voltage range for high voltage part v dd2 to v ss : C 2.5 to 4.5 v. lcd supply voltage range v lcd to v ss : C 4.5 to 9.0 v. low power consumption (typical 90 m a), suitable for battery operated systems external reset temperature compensation of v lcd temperature range: t amb = - 40 to +85 c manufactured in n-well silicon gate cmos process. 2 applications battery powered telecommunication systems. 3 general description the om6211 is a low power cmos lcd row/column driver, designed to drive a dot matrix graphic display of 48 rows and 84 columns. all necessary functions for the display are provided in a single chip, including on-chip generation of lcd supply and bias voltages, resulting in a minimum of external components and low power consumption. the om6211 interfaces to microcontrollers via a 3-line serial interface. 4 ordering information type number package name description version om6211u/2/f1 tray chip with bumps in tray -
2002 jan 17 4 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 5 block diagram handbook, full pagewidth mgu272 display data ram 48 84 bits data latches column drivers shift register reset row drivers col0 to col83 om6211 row0 to row47 84 3 t4, t5, t6 timing generator serial interface control display address counter command decoder oscillator osc address counter sce sdin sclk sdout v lcdout v lcdsense v lcdin v ss2 v ss1 v dd1 v dd2 v dd3 v lcd generator bias voltage generator res 48 2 id3, id4 mx 3 t1, t2, t3 5 v os [ 4:0 ] fig.1 block diagram.
2002 jan 17 5 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 6 pinning symbol pad description v os4 3 input pin 4 for v lcd calibration v os3 4 input pin 3 for v lcd calibration v os2 5 input pin 2 for v lcd calibration v os1 6 input pin 1 for v lcd calibration v os0 7 input pin 0 for v lcd calibration t6 8 to 11 test input 6 res 16 external reset input (active low) t5 17 test input 5 t4 18 test input 4 t3 19 test output 3 t2 20 test output 2 t1 21 test output 1 sce 22 chip enable input (active low) v ss2 23 to 30 ground v ss1 31 to 38 ground osc 40 oscillator input sdout 41 serial data output sdin 42 serial data input sclk 43 serial clock input id4 44 module identi?cation input id3 45 module identi?cation input mx 46 horizontal mirroring input v dd1 47 to 52 logic supply voltage v dd2 53 to 60 voltage multiplier supply voltage v dd3 61 to 64 voltage multiplier supply voltage v lcdsense 65 v lcd generator regulation input v lcdout 66 to 72 v lcd generator output v lcdin 73 to 78 lcd supply voltage input row 0 to row 23 89 to 112 lcd row driver outputs col0to col 83 113 to 196 lcd column driver outputs row 47 to row 24 197 to 220 lcd row driver outputs 1, 12 to 15, 39, 79, 81 to 88 and 221 to 225 dummy pads symbol pad description 7 pin functions 7.1 row 0 to row 47 row driver outputs these pads output the display row signals. 7.2 col 0 to col 83 column driver outputs these pads output the display column signals. 7.3 v ss1 and v ss2 : negative power supply rails negative power supply rails v ss1 and v ss2 must be connected together, hereafter referred to as v ss . when a pin has to be connected externally to v ss , then pin v ss1 should be used. 7.4 v dd1 to v dd3 : positive power supply rails positive power supply rails: v dd1 for logic supply, v dd2 and v dd3 for voltage multiplier. v dd2 and v dd3 must be connected together, hereafter referred to as v dd2 . 7.5 v lcdout , v lcdin and v lcdsense : lcd power supply if the internal v lcd generator is used, then all three pins must be connected together. if not (v lcd generator is disabled and an external voltage is applied to v lcdin ), then v lcdout must be left open-circuit, v lcdsense must be connected to v lcdin , v dd2 and v dd3 should be applied according to the specified voltage range. the following settings are also required: hve = 0, s 1 = 1 and s 0 =0. 7.6 v os4 to v os0 : calibration inputs five pull-up input pins for on-glass v lcd calibration. each pin may be connected to v ss , which corresponds to logic 0, or left open-circuit, which corresponds to logic 1. all five pins define a 5-bit twos complement number ranging from - 16 to 15 decimal (from 10000 to 01111). the default value, with all pins connected to v ss , is 0 decimal (00000).
2002 jan 17 6 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 in order to reduce current consumption related to the pull-up circuitry, the 5-bit number is stored in a register when exiting the power-down mode. the pull-up circuitry is then disabled. additionally, the register is refreshed by each hve command. 7.7 sdin: serial data input serial data input. 7.8 sdout: serial data output serial data output (3-state, push-pull). if bidirectional data transmission is required, sdout and sdin should be connected externally. if the read mode is not used, sdout should be left open-circuit. 7.9 sclk: serial clock input serial clock input. 7.10 sce: chip enable chip enable input, active low. if sce is high, the sclk pulses are ignored. 7.11 osc: oscillator external clock input. the external clock is active only in a special test mode, so in the application it is not available. in normal mode (the internal on-chip oscillator used) this input must be connected to v ss . if osc is held high, the internal oscillator is disabled. 7.12 mx: horizontal mirroring horizontal mirroring input. when mx = 1 the x address space is mirrored. 7.13 id3 and id4: identi?cation inputs lcd module identification inputs. their state can be read out via the serial interface in order to identify the module version. 7.14 res: reset external reset pin. when low the chip will be reset as defined in section 9.1. the initialization by the res pin is always required during power-on. timing for the res pin is illustrated in fig.18. 7.15 t1, t2, t3, t4, t5 and t6: test pins test pins. in the application t4 and t5 must be connected to v ss . t1, t2, t3 and t6 must be left open-circuit (t6 has a pull-down resistor). 8 block diagram functions 8.1 oscillator the on-chip oscillator provides the clock signal for the display system. it has no external components. 8.2 serial interface control detects the serial interface protocol, commands and display data bytes. the serial interface converts the data input (serial-to-parallel) as well as the output bits. 8.3 command decoder decodes all commands. 8.4 display data ram (ddram) the om6211 contains a 48 84 bit static ram which stores the display data. the ram is divided into six banks of 84 bytes (6 8 84 bits). during ram access, data is transferred to the ram via the serial interface. there is a direct correspondence between the x address and column output number. 8.5 timing generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not disturbed by operations of the serial interface. 8.6 address counter (ac) the address counter assigns addresses to the display data ram for writing. the x address (x 6 to x 0 ) and the y address (y 2 to y 0 ) are set separately. after a write operation the address counter is automatically incremented by 1. 8.7 display address counter the display is generated by continuously shifting rows of ram data to the dot matrix lcd via the column outputs. the display status (all dots on/off, normal/inverse video) is set via the serial interface. 8.8 v lcd generator a voltage multiplier (charge pump) with a programmable number of stages. internal capacitors are used for the voltage multiplier, therefore only decoupling capacitors for v lcd and v dd2 are required.
2002 jan 17 7 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 8.9 bias voltage generator generates 4 intermediate lcd bias voltages. the bias system is selectable; see section 9.9. 8.10 lcd row and column drivers the om6211 contains 48 row and 84 column drivers, which connect the appropriate lcd bias voltages in sequence to the display in accordance with the data to be displayed. figure 3 shows typical waveforms. 8.11 reset a reset initializes the chip. it can be performed either by the res pin being low or by a command. 9 functional description the om6211 is a low power lcd driver designed to interface with microprocessors/microcontrollers and a wide variety of lcds. the host microprocessor or microcontroller and the om6211 are connected via a serial interface. the internal oscillator requires no external components. the appropriate intermediate bias voltages for the multiplexed lcd waveforms are generated on-chip. the only other connections required to complete the system are to the power supplies (v dd1 , v dd2 , v ss and v lcd ) and suitable capacitors for decoupling v lcd and v dd2 . handbook, full pagewidth 84 column drivers 48 row drivers lcd panel mgu273 host microprocessor/ microcontroller v ss v ss1, 2 v lcd v dd1 v dd2, 3 v dd1 res sce sclk sda v ss v dd2 om6211 fig.2 typical system configuration.
2002 jan 17 8 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 9.1 reset the om6211 has no internal power-on reset, only external reset and reset by command. after power-on an external reset is required. a reset initiated either from the res pin or by command will initialize the chip to the following starting conditions: power-down mode (don = 0 and dal = 1): C internal oscillator stopped C the v lcd generator (hv generator) is switched off (hve = 0) and v lcdout is 3-state C display is off and all lcd outputs are internally connected to v ss (don = 0) C display all points is on (dal = 1). serial interface initialized; write mode display normal video (e = 0) address counter x 6 to x 0 =0;y 2 to y 0 = 0; display start line z 5 to z 0 = 0; no y mirroring (my = 0) bias system 1 7 (bs 2 to bs 0 = 100) v lcd selection v pr7 to v pr0 =0 voltage multiplication factor 4 (s 1 and s 0 = 10) temperature control mode tc3 (tc 1 and tc 0 = 11) frequency not calibrated and oc = 0 ram data is unchanged (after power-up undefined). 9.2 power-down the chip is in power-down mode if the display is off (don = 0) and display all points is on (dal = 1), regardless of the order in which both bits are set. during the power-down mode almost all static currents are switched off (no internal oscillator, no timing and no lcd segment drive system), and all lcd outputs are internally connected to v ss . the v lcd generator is switched off (but hve is not affected). the serial interface function remains. ram data is unchanged. when exiting the power-down mode, the v os value is stored in a register. 9.3 lcd voltage selector the practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10% contrast. 9.4 oscillator the internal logic operation and the multi-level drive signals of the om6211 are clocked by the built-in rc oscillator. no external components are required. the oscillator is in operation as long as the chip is not in power-down mode. 9.5 timing the timing of the om6211 organizes the internal data flow of the device. the timing also generates the lcd frame frequency that is derived from the clock frequency generated by the internal clock generator. 9.6 column driver outputs the lcd drive section includes 84 column outputs, which should be connected directly to the lcd. the column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. if less than 84 columns are required, the unused column outputs should be left open-circuit. 9.7 row driver outputs the lcd drive section includes 48 row outputs, which should be connected directly to the lcd. if less than 48 rows are required, the unused row outputs should be left open-circuit.
2002 jan 17 9 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 9.8 drive waveforms mgu274 row 0 r0 (t) row 1 r1 (t) col 0 c0 (t) col 1 c1 (t) 0 v 0 v v 3 - v ss frame n frame n + 1 01234567 8... ... 47 01234567 8... ... 47 v state1 (t) v state1 (t) v state2 (t) v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v lcd - v 2 v 4 - v 5 v ss - v 5 v 4 - v lcd v 3 - v 2 - v lcd 0 v 0 v v 3 - v ss v state2 (t) v lcd v lcd - v 2 v 4 - v 5 v 4 - v lcd v 3 - v 2 v ss - v 5 - v lcd fig.3 typical lcd driver waveforms. v state1 (t) = c1(t) - r0(t). v state2 (t) = c1(t) - r1(t).
2002 jan 17 10 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 9.9 bias system the bias voltage levels are set in the ratio of r-r-nr-r-r. different multiplex rates require different factors of n. this is programmed by bs 2 to bs 0 . for optimum bias values, n can be calculated from the following equation: ; where mux rate is 48. changing the bias system from the optimum setting will have a consequence on the contrast and viewing angle. one reason to depart from the optimum would be to reduce the required v lcd voltage. a compromise between contrast and v lcd must be found for any particular application. in the om6211 one of three possible values of the bias system can be selected. the value 1 7 is default. n mux rate 3 C = table 1 programming the required bias system table 2 lcd bias voltages for 1 6 bias, 1 7 bias and 1 8 bias. 9.10 voltage multiplier control the om6211 incorporates a software configurable voltage multiplier. after reset ( res) the voltage multiplier is set to 4v dd2 . other voltage multiplier factors are set via the serial interface (s 1 and s 0 ). table 3 hv generator multiplication bs 2 bs 1 bs 0 n bias mode typical mux rates 0114 1 8 1 : 55 and 1 : 48 1003 1 7 1:33 1012 1 6 1:24 symbol bias voltage for 1 6 bias for 1 7 bias for 1 8 bias v1 v lcd v lcd v lcd v2 5 6 v lcd 6 7 v lcd 7 8 v lcd v3 4 6 v lcd 5 7 v lcd 6 8 v lcd v4 2 6 v lcd 2 7 v lcd 2 8 v lcd v5 1 6 v lcd 1 7 v lcd 1 8 v lcd v6 v ss v ss v ss s 1 s 0 multiplication 002v dd2 013v dd2 104v dd2 1 1 not available
2002 jan 17 11 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 9.11 temperature compensation due to the temperature dependency of the liquid crystals viscosity, the lcd controlling voltage (v lcd ) must be increased at lower temperatures to maintain optimum contrast. figure 4 shows v lcd as a function of temperature for a typical high multiplex rate liquid. in the om6211 the temperature coefficient of v lcd can be selected from 4 values by setting bits tc 1 and tc 0 , see tables 4 and 8. handbook, full pagewidth mgt848 t v lcd fig.4 v lcd as a function of liquid crystal temperature (typical values). 9.12 v lcd generator the binary number v op representing the operating voltage can be set by the serial interface command and can be adjusted (calibrated) by 5 input pins according to the following formula: (1) where: v pr is an 8-bit unsigned number set by the serial interface command v os is a 5-bit twos complement number set by the 5 input pins v os4 to v os0 , see table 9 v op is an 8-bit unsigned number used internally for generation of the lcd supply voltage v lcd . to avoid numerical overflow the allowed values of v pr should be limited to the range 32 to 225 (decimal). the corresponding voltage at the reference temperature, t nom , can be calculated as follows: (2) the generated voltage at v lcd is dependent on the temperature, programmed temperature coefficient (tc) and the programmed voltage at the reference temperature (t nom ). (3) t nom , a and b for each temperature coefficient are given in table 4. the maximum voltage that can be generated is dependent on the voltage of v dd2 and the display load current. as the programming range for the internally generated v lcd allows values above the maximum allowed v lcd , the user has to ensure while setting the v pr register and selecting the temperature compensation, that under all conditions and including all tolerances the v lcd limit of maximum 9 v will never be exceeded. for a particular liquid crystal, the optimum value of v lcd can be calculated for a given multiplex rate. for a mux rate of 1 : 48, the optimum operating voltage of the liquid crystal can be calculated as follows; (4) where v th is the threshold voltage of the liquid crystal used. v op v pr v os + = v lcd(tnom) av op b + () = v lcd av op + b () 1tc tt nom C () + [] = v lcd 148 + 21 1 48 ---------- C ? ?? --------------------------------------- v th 6.06 v th = =
2002 jan 17 12 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 table 4 typical values for parameters of the hv generator programming example: to achieve v lcd = 8.3 v at temperature t nom for tc3 it is necessary to set v pr = 180 (decimal). example for calibration: before calibration v pr = 180 was applied, but the measured voltage was v lcd = 8.4 v. to decrease v lcd by 100 mv the best value for v os is - 4 decimal (11100 binary in the twos complement notation). so after calibration with v os = - 4 the proper v pr value is still 180. as v os is used for calibration and the default value is 0, for selecting the value of v pr it can always be considered that v os =0. symbol tc0 tc1 tc2 tc3 unit a 4.57 4.28 4.04 3.79 v b 30.0 28.0 26.5 25.0 mv t nom 27 27 27 27 c tc 0 - 0.25 - 0.5 - 0.75 10 -3 / c handbook, full pagewidth mgt847 00 01 02 a v lcd v op 03 04 05 06 . . . . . . fd fe ff b fig.5 v lcd programming of om6211. v op7 to v op0 programming, (00h to ffh).
2002 jan 17 13 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 10 initialization 10.1 initialization sequence after reset ( res) it is recommended to initialize the v lcd generator using the following sequence; a starting state of hve = 0, don = 0 and dal = 1 is assumed: 1. set the required v op and, if required, the voltage multiplier s 1 and s 0 2. set dal = 0 to leave the power-down state (in order to precharge the charge pump v lcd is set to v dd2 ) 3. wait for at least 1 ms and set hve = 1 to switch-on the v lcd generator 4. set don = 1 to switch the display on. 10.2 frame frequency calibration (oc) the om6211 incorporates frame frequency calibration via software. the calibration is achieved by tuning the internal oscillator. after reset the frame frequency calibration is disabled (oc = 0). the calibration can only be performed if the driver is not in power-down mode. the calibration is started by setting oc = 1 via the serial interface (start command) and will be stopped by setting oc = 0 (stop command). the time between start and stop of the calibration must be 200 ms to give a frame frequency of 80 hz. any variation in calibration time (deviation from 200 ms) results in a corresponding variation in frame frequency. during calibration all other commands are allowed. the calibration may be repeated and is always performed with the previously calibrated frequency. through repeated calibrations a better accuracy can be expected and, most especially, the temperature drift can be compensated for. a minimum time delay of 500 ms between consecutive calibration events is necessary (between stop and start). the calibration will always be performed if the calibration time is between 190 and 210 ms. if, however, the calibration time is lower then 58 ms or higher than 690 ms (or the stop command does not occur at all), the calibration attempt is ignored and the previously selected frequency is maintained. for the remaining values of the calibration time (from 58 to 190 ms and from 210 to 690 ms) it cannot be determined if the calibration will be performed or ignored. 11 addressing 11.1 addressing data is downloaded in bytes into the ram matrix of om6211 as illustrated in figs 6 and 7. the display ram has a matrix of 48 84 bits. the columns are addressed by the address pointer. the address ranges are x = 0 to 83 (1010011) and y = 0 to 5 (101). addresses outside of these ranges are not allowed. the x address increments after each byte (see fig.7). after the last x address (x = 83) x wraps around to 0 and y increments to address the next row. after the very last address (x = 83 and y = 5) the address pointers wrap around to address x = 0 and y = 0. the selection of the mx input allows horizontal mirroring: when mx = 1, the x address space is mirrored (see fig.6). when mx = 0 the mirroring is disabled. mx affects data only during writing to the ram, so after a change of mx ram data must be re-written. the my bit allows vertical mirroring: when my = 1, then the y address space is mirrored. my does not affect the ram content, but defines the way ram data is written to the display. a change of my has an immediate effect on the display. vertical scrolling of the display is controlled by the z address with a range from 0 to 47 (101111). the z address specifies which rows of the ram are output to which row outputs. the value of the z address defines which row of the ram will be row 0 of the display (which is normally the top row of the display). for example, if the z address is set to 31 (see fig.8), then the data displayed on row 0 of the display will be the data from row 31 of the ram and the data on row 1 will be from row 32 of the ram. when the my is active (my = 1), then the z address defines which row of the ram is written to row 47 of the display. for example, when the z address is set to 31, row 47 of the display would come from row 31 of the ram and row 46 from row 32 of the ram (see fig.9). the z address does not affect the ram content, but defines the way ram data is written to the display. a change of z address has an immediate effect on the display.
2002 jan 17 14 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 handbook, full pagewidth mgu275 0 5 0 83 83 0 x address y address lsb msb mx = 0 mx = 1 fig.6 ram format, addressing. handbook, full pagewidth mgt845 012 84 85 86 168 169 170 252 253 254 336 337 338 420 421 422 0 5 503 083 x address y address fig.7 sequence of writing data bytes into ram.
2002 jan 17 15 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... row 0 row 1 row 2 row 3 row 4 row 5 row 6 row 7 row 8 row 9 row 10 row 11 row 12 row 13 row 14 row 15 row 16 row 17 row 18 row 19 row 20 row 21 row 22 row 23 row 24 row 25 row 26 row 27 row 28 row 29 row 30 row 31 row 32 row 33 row 34 row 35 row 36 row 37 row 38 row 39 row 40 row 41 row 42 row 43 row 44 row 45 row 46 row 47 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 z address = 31 0 y address z address when my = 0 ram display mgu276 1 2 3 4 5 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 fig.8 programming the z address when my = 0.
2002 jan 17 16 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 z address = 31 0 y address z address with my = 1 ram display mgu277 1 2 3 4 5 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 row 0 row 1 row 2 row 3 row 4 row 5 row 6 row 7 row 8 row 9 row 10 row 11 row 12 row 13 row 14 row 15 row 16 row 17 row 18 row 19 row 20 row 21 row 22 row 23 row 24 row 25 row 26 row 27 row 28 row 29 row 30 row 31 row 32 row 33 row 34 row 35 row 36 row 37 row 38 row 39 row 40 row 41 row 42 row 43 row 44 row 45 row 46 row 47 fig.9 programming the z address when my = 1.
2002 jan 17 17 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 top of lcd mgt842 ddram bank 0 bank 1 bank 2 r0 r8 r16 r24 r32 r40 r47 bank 3 bank 4 bank 5 lcd fig.10 ddram to display mapping (z = 0).
2002 jan 17 18 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 11.2 serial interface the serial interface is a 3-line bidirectional interface for communication between the microcontroller and the lcd driver chip. the 3 lines are: sce (chip enable), sclk (serial clock) and sda (serial data). the om6211 is connected to sda by two pins: sdin (data input) and sdout (data output) connected together. 11.2.1 w rite mode the write mode of the interface means that the microcontroller writes commands and data to the om6211. each data packet contains a control bit d/ c and a transmission byte. if d/ c is low, the following byte is interpreted as a command byte (see table 5). if d/ c is high, the following byte is stored in the display data ram. after every data byte the address counter is incremented automatically. figure 11 shows the general format of the write mode and the definition of the transmission byte. every command can be sent in any order to the om6211. the msb of a byte is transmitted first. the serial interface is initialized when sce is high. in this state, sclk clock pulses have no effect and no power is consumed by the serial interface. a falling edge on sce enables the serial interface and indicates the start of a data transmission. figures 12, 13 and 14 show the protocol of the write mode: when sce is high, sclk clocks are ignored: during the high time of sce the serial interface is initialized (see fig.12) at the falling edge of sce sclk must be low (see fig.16); for the transmission of each data bit a rising and then a falling edge of sclk is necessary sdin is sampled at the rising edge of sclk d/ c indicates whether the byte is a command (d/ c=0) or ram data (d/ c = 1); it is sampled with the first rising sclk edge if sce stays low after the last bit of a command or data byte, the serial interface expects the d/ c bit of the next byte at the next rising edge of sclk (see fig.13) a reset pulse with res interrupts the transmission. the data being written into the ram may be corrupted. the registers are cleared. if sce is low after the rising edge of res, the serial interface is ready to receive the d/ c bit of a command or data byte (see fig.14). handbook, full pagewidth d/c db7 db6 db5 db4 db3 transmission byte (tb) (command byte or data byte) db2 db1 db0 msb lsb mgu278 tb d/c tb d/c tb d/c fig.11 serial data stream, write mode.
2002 jan 17 19 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 handbook, full pagewidth sce d/c sclk sdin db7 db6 db5 db4 db3 db2 db1 db0 mgu279 fig.12 write mode: a control bit followed by a transmission byte. handbook, full pagewidth sce sclk sdin db7 d/c db6 db5 db4 db3 db2 db1 db0 mgu280 db7 d/c db6 db5 db4 db3 db2 db1 db0 d/c fig.13 write mode: transmission of several bytes. handbook, full pagewidth mgu281 sce res sclk sdin db7 d/c db6 db5 db4 db7 db7 db6 db5 db4 db3 db2 db1 db0 db6 d/c d/c fig.14 write mode: interrupted by reset ( res).
2002 jan 17 20 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 11.2.2 r ead mode in the read mode of the interface the microcontroller reads data from the om6211. to do so the microcontroller first has to send the read status command, and then the following byte is transmitted in the opposite direction (using sdout). after that sce is required to go high before a new command is sent (see fig.15). the om6211 samples the sdin data on the rising edges of sclk, but shifts sdout data on the falling edges of sclk. thus the microcontroller is supposed to read sdout data on the rising edges of sclk. after the read status command has been sent, the sdin line must be set to 3-state not later then the falling sclk edge of the last bit (see fig.15). the 8th read bit is shorter than the others because it is terminated by the rising edge of sclk (see fig.15). the last rising edge of sclk sets sdout to 3-state after the delay time t 3 (see section 10.1 and fig.17). there are 5 bits of information only that can be read by the microcontroller (see table 7). two of them are chip identification bits and have fixed values. the next two bits are lcd module identification bits and can be set by connecting the id3 and id4 pins to v dd1 or v ss . the fifth bit is the v lcd voltage monitor bit vm. it indicates that the charge pump is running and the voltage level of v lcd is sufficient to provide enough contrast of the display (vm = 1). if the v lcd generator cannot produce a voltage defined by v op , then vm = 0. vm has a valid value 45 ms after a delay time of approximately 45 ms starting from the time the v lcd generator has been switched on (by setting hve = 1). this delay time is dependent on the external v lcd decoupling capacitor (here 100 nf is assumed). for more details concerning the vm bit see chapter 22 the reading out of the chip identification bits and module identification bits can be used to implement different initialization schemes for different applications. the reading out of vm can be used to check the proper electrical contacts of the lcd module. one read status command enables one status bit to be read, i.e. 5 commands are needed to read the status of all 5 bits. the first 4 bits of the read byte (db7 to db4) are always equal to the corresponding status bit and the next 4 bits (db3 to db0) are equal to the complement of this bit. as stated before the sdout data is supposed to be read on the rising edge of sclk. care must be taken, however, when running the sclk at maximum frequency. because of the access time limit t 2 (see section 10.1 and fig.17) it might happen that the first bits of each group (db7 to db4 and db3 to db0) are not valid at the time of the corresponding sclk edges. thus it is recommended to read the bits db4 and db0 only. handbook, full pagewidth mgu282 sce sclk sdin sdout db7 d/c db6 db5 db4 db7 db6 db5 db4 db3 db2 db1 db0 db3 db2 db1 db0 d/c fig.15 read mode.
2002 jan 17 21 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 12 instructions 12.1 instruction set table 5 instruction set; see notes 1 and 2 and table 6 notes 1. x = dont care. 2. db7 = msb. instruction d/ c command byte description db7 db6 db5 db4 db3 db2 db1 db0 nop 0 1 1 1 0 0 0 1 1 no operation reset 0 1 1 1 0 0 0 1 0 software reset write data 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 write data to display ram read status 0 1 1 0 1 1 sb2 sb1 sb0 read one of the status bits; table 7 display control 0 1 0 1 0 1 1 1 don display on/off; see table 6 0 1 0 1 0 0 1 1 e normal, reverse mode; see table 6 0 1 0 1 0 0 1 0 dal all pixels on; see table 6 0 1 1 0 0 my x x x mirror y; see table 6 address commands 010110y 2 y 1 y 0 set y address; 0 y 5 00 0 0 1 xx 6 x 5 x 4 set x address; 0 x 83 00 0 0 0x 3 x 2 x 1 x 0 set x address; 0 x 83 display start line 0 0 1 z 5 z 4 z 3 z 2 z 1 z 0 set start row, 0 z 47 power control 0 0 0 1 0 1 hve hve hve switch hv-gen on/off; see table 6 01 0 0v pr4 v pr3 v pr2 v pr1 v pr0 lower part of v pr ; see equation (1) 000100v pr7 v pr6 v pr5 higher part of v pr frame calibration 0 1 0 1 0 1 1 0 oc frame calibration start/stop; see table 6 tc 0 0 0 1 1 1 0 tc1 tc0 set temperature coef?cient; see table 8 hv-gen stages 0 0 0 1 1 1 1 s 1 s 0 set multiplication factor; see table 3 bias system 0 0 0 1 1 0 bs2 bs1 bs0 set bias system; see table 1 test 0 1 0 1 0 1 0 0 x reserved 0 1 1 1 0 1 0 1 1 reserved 0 1 1 1 0 1 1 0 0 reserved 0 1 1 1 0 1 1 1 1 reserved
2002 jan 17 22 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 table 6 explanations for symbols in table 5 bit logic 0 logic 1 don display off display on dal normal display (only if don = 1) all pixels on e normal display inverse video mode (only if dal = 0) hve v lcd generator (hv generator) is switched off v lcd generator is switched on my no y mirroring y mirroring oc stop frame frequency calibration start frame frequency calibration table 7 read status table 8 temperature coef?cients table 9 v os values in twos complement notation sb[2:0] read status bit description 010 id1 ?xed value 0 011 id2 ?xed value 1 100 id3 de?ned by input pin id3 101 id4 de?ned by input pin id4 111 vm vm tc[1:0] 00 tc0 01 tc1 10 tc2 11 tc3 decimal binary +0 00000 +1 00001 +2 00010 +3 00011 +4 00100 +5 00101 +6 00110 +7 00111 +8 01000 +9 01001 +10 01010 +11 01011 +12 01100 +13 01101 +14 01110 +15 01111 - 1 11111 - 2 11110 - 3 11101 - 4 11100 - 5 11011 - 6 11010 - 7 11001 - 8 11000 - 9 10111 - 10 10110 - 11 10101 - 12 10100 - 13 10011 - 14 10010 - 15 10001 - 16 10000 decimal binary
2002 jan 17 23 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 13 limiting values in accordance with the absolute maximum rating system (iec 60134); notes 1 and 2. notes 1. stresses above those listed under limiting values may cause permanent damage to the device. 2. parameters are valid over operating temperature range unless otherwise specified. all voltages are referenced to v ss unless otherwise specified. 3. v ss =0v. 14 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is recommended to take normal precautions appropriate to handling mos devices (see handling mos devices ). 15 dc characteristics v dd1 = 1.7 to 2.3 v; v dd2 = 2.5 to 4.5 v; v ss =0v; v lcd = 4.5 to 9.0 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +6.5 v v lcd lcd supply voltage - 0.5 +9.0 v v i , v o input/output voltage (any input/output) - 0.5 v dd1 + 0.5 v i i , i o dc input or output current - 10 +10 ma i dd , i ss , i lcd v dd , v ss or v lcd current note 3 - 50 +50 ma p tot total power dissipation per package - 100 mw p out power dissipation per output - 10 mw t stg storage temperature - 65 +150 c t j(max) maximum junction temperature - 150 c symbol parameter conditions min. typ. max. unit supplies v dd1 logic supply voltage 1.7 1.8 2.3 v v dd2, v dd3 supply voltage for voltage multiplier note 1 2.5 2.78 4.5 v v lcdin lcd supply voltage 4.5 - 9.0 v v lcdout generated lcd supply voltage note 2 6.8 -- v v lcd(tol) tolerance of generated v lcd with calibration; note 3 - 70 - +70 mv i dd1 v dd1 supply current power-down mode; note 4 - 210 m a normal mode; note 4 - 12 -m a i dd2, i dd3 v dd2 and v dd3 supply current power-down mode; note 4 - 15 m a normal mode; note 4 - 78 -m a i dd(tot) total supply current (v dd1 and v dd2, v dd3 ) normal mode; note 4 - 90 -m a normal mode; note 5 - 120 -m a
2002 jan 17 24 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 notes 1. v dd2 is always equal v dd3 . 2. conditions are: v dd2 = 2.5 v, voltage multiplier = 3v dd2 , bias system 1 6 , v lcd output is loaded by 10 m a, t amb =25 c. 3. valid for values of temperature, v pr and tc used at the calibration. 4. conditions are: v dd1 = 1.8 v, v dd2 = 2.78 v, v lcd = 6.8 v, voltage multiplier = 3v dd2 , bias system 1 6 , inputs at v dd1 or v ss , serial interface inactive, internal v lcd generation, v lcd output is loaded by 10 m a; t amb =25 c. 5. conditions are: v dd1 = 1.8 v, v dd2 = 2.78 v, v lcd = 8.3 v, voltage multiplier = 4v dd2 , bias system 1 7 , inputs at v dd1 or v ss , serial interface inactive, internal v lcd generation, v lcd output is loaded by 10 m a; t amb =25 c. 6. load current 10 m a, outputs tested one at a time. logic v il low-level input voltage v ss - 0.3v dd1 v v ih high-level input voltage 0.7v dd1 - v dd1 v i ol low-level output current (sdout) v ol = 0.4 v; v dd1 = 1.8 v 0.5 -- ma i oh high-level output current (sdout) v oh = 1.4 v; v dd1 = 1.8 v --- 0.5 ma i l leakage current v i =v dd1 or v ss - 1 - +1 m a column and row outputs r o(col) column output resistance (col 0 to col 83) note 6 - 420k w r o(row) row output resistance (row 0 to row 47) note 6 - 420k w v bias(col) bias tolerance (col 0 to col 83) - 100 0 +100 mv v bias(row) bias tolerance (row 0 to row 47) - 100 0 +100 mv calibration inputs r on(vos) external resistance between a v os pin and the v ss1 pin for logic 0 -- 10 k w r off(vos) external resistance between a v os pin and the v ss1 pin for logic 1 5 -- m w symbol parameter conditions min. typ. max. unit
2002 jan 17 25 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 16 ac characteristics v dd1 = 1.7 to 2.3 v; v dd2 = 2.5 to 4.5 v; v ss =0v; v lcd = 4.5 to 9.0 v; t amb = - 40 to +85 c; unless otherwise speci?ed. notes 1. 2. temperature range t amb = - 30 to +70 c. 3. calibrated at v dd1 = 1.8 v and t amb =25 c, valid for both otp calibration and software calibration, exact calibration time assumed. 4. measured at v dd1 = 1.8 v, temperature range t amb = - 30 to +70 c. 5. measured at v dd1 = 1.8 v, t amb =25 c. 6. it is recommended that res is low before v dd1 goes high 7. t h5 is the time from the previous sclk rising edge (irrespective of the state of sce) to the falling edge of sce (see fig.16). 8. capacitive load at pin sdout less than 50 pf. symbol parameter conditions min. typ. max. unit f osc(int) internal oscillator frequency note 1 - 251 - khz f frame frame frequency uncalibrated; note 2 46 80 142 hz calibrated; notes 3 and 4 63 80 97 hz calibrated; notes 3 and 5 75 80 85 hz t vhrl v dd1 to res low see fig.18; note 6 0 - 30 ms t rw reset low pulse width see fig.18 1000 -- ns t r(op) end of reset pulse to interface being operational -- 1000 ns serial interface timing f sclk clock frequency 0 - 4.00 mhz t cyc clock cycle sclk 250 -- ns t pwh1 sclk pulse width high 120 -- ns t pwl1 sclk pulse width low 100 -- ns t s2 sce set-up time 60 -- ns t h2 sce hold time 100 -- ns t pwh2 sce minimum high time 100 -- ns t h5 sce start hold time note 7 100 -- ns t s1 sdin set-up time 100 -- ns t h1 sdin hold time 100 -- ns t 2 sdout access time note 8 0 - 450 ns t 3 sdout disable time 25 - 450 ns t 4 sce hold time 100 -- ns t 5 sce hold time 20 -- ns f frame f osc 3136 ------------- =
2002 jan 17 26 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 16.1 serial interface timing handbook, full pagewidth mgu283 t h1 t pwh1 t pwl1 t s1 t s2 t 5 t s2 t h2 t h5 t cyc (t h5 ) t pwh2 sce sclk sdin fig.16 serial interface timing: write mode. handbook, full pagewidth mgu284 t 4 t 3 t s1 t 2 sce sclk sdin sdout t 2 t 2 t h1 fig.17 serial interface timing: read mode.
2002 jan 17 27 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 16.2 reset timing t r(oper) sce handbook, full pagewidth mgu285 t vhrl t rw res v dd1 fig.18 reset timing. 17 application information the pinning of the om6211 is optimized for single plane wiring e.g. for chip-on-glass display modules. display size: 48 84 pixels. the required minimum value for the two external capacitors (c ext ) in an application with the om6211 is 100 nf (min.). higher capacitor values are recommended for ripple reduction. handbook, full pagewidth mgu286 4 display 48 84 pixels i/o c ext om6211 84 24 24 v dd2 v dd1 v ss v lcd fig.19 application diagram.
2002 jan 17 28 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 18 module maker programming the one time programmable (otp) technology has been implemented on the om6211. it enables the module maker to program some extended features of the om6211 after it has been assembled on an lcd module. programming is made under the control of the serial interface and the use of one special pin. this pin must be made available on the module glass but needs not to be accessed by the set maker. as the module maker programming is an extension of the normal functions of the om6211 it will not be effective until specifically instructed with the enable otp command. the om6211 features 3 module maker programmable parameters: v lcd calibration v pr default value seal bit. 18.1 v lcd calibration the first feature included is the ability to tune the v lcd voltage with a 5-bit code. this code is implemented in twos complement notation giving rise to a positive or negative offset to the v pr register. this is in the same manner as the on-glass calibration pins v os (laser trim pins). in theory, both may be used together but it is recommended that the laser trim pins are tied to v ss when otp calibration is being used. this will set them to a default offset of zero. if both are used then the addition of the two 5-bit numbers must not exceed a 5-bit result otherwise the resultant value will be undefined. the final adder in the circuit has underflow and overflow protection. in the event of an overflow, the output will be clamped to 255; and during an underflow the output will be clamped to 0. the final control to the high voltage generator, v op , will be the sum of all the calibration registers and pins. the v op equation (1) given in section 9.12 must be extended to include the otp calibration. (5) the additional offset applied to v lcd can be calculated from equation (2) and (5), where b is the step size as defined in table 4. (6) the possible mmvopcal 4 to mmvopcal 0 values are the same as the v os [4:0] values, see table 9. v op v pr v os mmvopcal ++ = v lcd offset v os mmvopcal + () b = handbook, full pagewidth mgu287 otp v lcd calibration: 5-bit offset mmvopcal [ 4:0 ] v op [7:0] range: 0 to + 255 range - 16 to + 15 range - 16 to + 15 range 0 to + 255 usable range + 32 to + 255 to high voltage generator laser trim pins: 5-bit offset v os [ 4:0 ] v pr register: 8-bit value v pr [ 7:0 ] + + fig.20 v lcd calibration.
2002 jan 17 29 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 18.2 v pr default value the second feature is an otp factory default setting for v pr . this is an 8-bit value from which the v pr register can be loaded using the load factory default command. the idea of this feature is to make it unnecessary for the set maker to specify the v pr value. the factory default may be overridden by the set maker in the normal fashion using the set v pr commands. handbook, full pagewidth mgu288 interface data load v pr via the interface load v pr from an otp default register. otp v pr default register, 8-bit value v pr register: 8-bit value + fig.21 load v pr register: default or specified via interface. 18.3 seal bit the module maker programming is performed in a special mode: the calibration mode (calmm). this mode is entered via a special interface command, calmm. to prevent wrongful programming, a seal bit has been implemented which prevents the device from entering the calibration mode. this seal bit, once programmed, cannot be reversed, thus further changes in programmed values are not possible. however, it is possible to disable all programmed values by not applying the enable otp command. applying the programming voltages when not in calmm mode will have no effect on the programmed values. table 10 seal bit de?nition 18.4 otp architecture the otp circuitry in the om6211 contains 14 bits of data: 5 for v lcd calibration, 8 for v pr default and 1 seal bit. the circuitry for 1-bit is called an otp slice, thus there are 14 otp slices. each otp slice consists of 2 main parts: the otp cell (a non-volatile memory cell) and the shift register cell (a flip-flop). the otp cells are only accessible through their shift register cells: on the one hand both reading from and writing to the otp cells is performed with the shift register cells, on the other hand only the shift register cells are visible to the rest of the circuit. the basic otp architecture is shown in fig.22. this otp architecture enables the following operations: 1. reading data from the otp cells. the content of the non-volatile otp cells is transferred to the shift register where it may affect the om6211 operation (provided it has been enabled by the enable otp command). 2. writing data to the otp cells. firstly, all 14 bits of data are shifted into the shift register via the serial interface. the content of the shift register is then transferred to the otp cells (there are some limitations related to storing data in these cells, see section 18.7). 3. checking calibration without writing to the otp cells. shifting data into the shift register allows the effects on the v lcd voltage to be observed. seal bit action 0 possible to enter calibration mode 1 calibration mode disabled
2002 jan 17 30 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 all otp circuitry of the om6211 is disabled until the enable otp command is given. once enabled, the reading of data from the otp cells is initiated by either: exit from power-down mode the refresh command. it should be noted that in both cases the reading operation needs up to 5 ms to complete. the shifting of data into the shift register is performed in a special mode called calmm. in the om6211 the calmm mode is entered through the calmm command. once in the calmm mode the data is shifted into the shift register via the serial interface at the rate of 1-bit per command. after transmitting the last (14th) bit and exiting the calmm mode the serial interface returns to the normal mode and all other commands can be sent. care should be taken that all 14 bits of data (or a multiple of 14) are transferred before exiting the calmm mode, otherwise the bits will be in the wrong positions. in the shift register the value of the seal bit is, like the others, always zero at reset. to ensure that the security feature works correctly, the calmm command is disabled until a refresh has been performed. once the refresh is completed, the seal bit value in the shift register is valid and permission to enter calmm mode can thus be determined. the 14 bits are shifted into the shift register in a predefined order: firstly the 8 bits of mmotpvop 7 to mmotpvop 0 , then the 5 bits of mmvopcal 4 to mmvopcal 0 and lastly the seal bit. the msb is always first, thus the first bit shifted is mmotpvop 7 and the two last bits are mmvopcal 0 and the seal bit. handbook, full pagewidth data to the circuit for configuration and calibration shift register flip-flop otp slice otp cell shift register shift register data input read data from the otp cell write data to the otp cell otp cells mgu289 fig.22 basic otp architecture.
2002 jan 17 31 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 18.5 serial interface commands these instructions are in addition to those indicated in table 5. table 11 additional instructions instruction d/ c command byte action db7 db6 db5 db4 db3 db2 db1 db0 enable otp 011101011 enable otp circuitry calmm 011101111 enter calmm mode load factory default 011101100 load mmotpvop 7 to mmotpvop 0 into v pr register power control (refresh) 000101hvehvehve set hve; force a refresh of the shift register 18.5.1 e nable otp this is a special instruction for the om6211 which enables all included otp circuitry. once enabled the mode can only be disabled via a reset. 18.5.2 calmm this instruction puts the device into the calibration mode. this mode enables the shift register for loading and allows programming of the non-volatile otp cells to take place. if the seal bit is set then this mode cannot be accessed and the instruction will be ignored. once in calibration mode all commands are interpreted as shift register data. the mode can only be exited by sending data with bit db7 set to logic 0. a reset will also clear this mode. each shift register data byte is preceded by d/ c = 0 and has only 2 significant bits, thus the remaining 6 bits are ignored. bit db7 is the continuation bit (db7 = 1 remain in calmm mode, db7 = 0 exit calmm mode). bit db0 is the data bit and its value is shifted into the otp shift register (on the falling edge of sclk). 18.5.3 l oad factory default the load factory default instruction is used to transfer the contents of the otp shift register bits mmotpvop 7 to mmotpvop 0 into the normal working register of v pr ; see fig.21. this is opposite to the calibration register mmvopcal 4 to mmvopcal 0 which is active immediately after a refresh. 18.5.4 r efresh the action of the refresh instruction is to force the otp shift register to re-load from the non-volatile otp cells. this instruction takes up to 5 ms to complete. during this time all other instructions may be sent, however, instructions requiring the output of the shift register (load factory default) should be avoided as the register contents may not be valid. in the om6211 the refresh instruction is associated to the set hve instruction so that the shift register is automatically refreshed every time the high voltage generator is enabled or disabled. it should be noted however, that if this instruction is sent while in power-down mode, then the hve bit is updated but the refreshing is ignored. 18.6 example of ?lling the shift register an example sequence of commands and data is shown in table 12. in this example the shift register is filled with the following data: mmvopcal = - 4 (11100b), mmotpvop = 19 (00010011b) and the seal bit is 0. it is assumed that the om6211 has just been reset. after transmitting the last bit the om6211 can exit or remain in calmm mode (see step 18). it should be noted that while in calmm mode the interface does not recognize commands in the normal sense. after this sequence has been applied it is possible to observe the impact of the data shifted in. this sequence is, however, not useful for otp programming because the number of bits with the value 1 is greater than that allowed for programming (see section 18.7). figure 23 shows the shift register after this action.
2002 jan 17 32 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 table 12 example sequence for ?lling the shift register; note 1 notes 1. x = dont care. 2. the data for the bits is not in the correct shift register position until all bits have been sent. step d/ c command byte action db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 1 1 0 1 0 1 1 send enable otp command 2 0 1 0 1 0 1 1 1 1 exit power-down (e.g. don = 1) 3 wait 5 ms for refresh to take effect. 4 0 1 1 1 0 1 1 1 1 enter calmm mode 5 0 1 x x x x x x 0 shift in data; mmotpvop 7 is ?rst bit; note 2 6 0 1 x x x x x x 0 mmotpvop 6 7 0 1 x x x x x x 0 mmotpvop 5 8 0 1 x x x x x x 1 mmotpvop 4 9 0 1 x x x x x x 0 mmotpvop 3 10 0 1 x x x x x x 0 mmotpvop 2 11 0 1 x x x x x x 1 mmotpvop 1 12 0 1 x x x x x x 1 mmotpvop 0 13 0 1 x x x x x x 1 mmvopcal 4 14 0 1 x x x x x x 1 mmvopcal 3 15 0 1 x x x x x x 1 mmvopcal 2 16 0 1 x x x x x x 0 mmvopcal 1 17 0 1 x x x x x x 0 mmvopcal 0 18 0 0 x x x x x x 0 seal bit; exit calmm mode an alternative ending could be to stay in calmm mode 18 0 1 x x x x x x 0 seal bit; remain in calmm mode handbook, full pagewidth msb lsb shifting direction 0 mgu290 mmvopcal[4:0] seal bit = 0 0 1 1 1 msb lsb 1 mmotpvop[7:0] otp shift register 1 0 0 0 0 0 1 fig.23 shift register contents after example sequence of table 12.
2002 jan 17 33 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 18.7 programming ?ow programming is achieved whilst in calmm mode and with the application of the programming voltages. as mentioned previously, the data for programming the otp cell is contained in the corresponding shift register cell. the shift register cell must be loaded with a logic 1 in order to program the corresponding otp cell. if the shift register cell contains a logic 0, then no action will take place when the programming voltages are applied. once programmed, an otp cell can not be un-programmed. an already programmed cell, that is an otp cell containing a logic 1, must not be re-programmed. the order for programming cells is not significant. however, it is recommended that the seal bit is programmed last. once this bit has been programmed it will not be possible to re-enter the calmm mode. during programming a substantial current flows in the v lcdin pin. for this reason it is recommended to program only one otp cell at a time. this is achieved by filling all but one shift register cells with logic 0. it should be noted that the programming specification refers to the voltages at the chip pins, contact resistance must therefore be considered by the user. an example sequence of commands and data for otp programming is shown in table 13. it is assumed that the om6211 has just been reset. table 13 example sequence for otp programming; note 1 note 1. x = dont care. step d/ c command byte action db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 1 1 0 1 0 1 1 send enable otp command 2 0 1 0 1 0 1 1 1 1 exit power-down (e.g. don = 1) 3 wait 5 ms for refresh to take effect 4 0 1 0 1 0 1 1 1 0 re-enter power-down (don = 0) 5 0 1 1 1 0 1 1 1 1 enter calmm mode 6 0 1 x x x x x x 0 shift in data. mmotpvop 7 7 0 1 x x x x x x 0 mmotpvop 6 8 0 1 x x x x x x 0 mmotpvop 5 9 0 1 x x x x x x 1 mmotpvop 4 (the only bit with the value 1) 10 0 1 x x x x x x 0 mmotpvop 3 11 0 1 x x x x x x 0 mmotpvop 2 12 0 1 x x x x x x 0 mmotpvop 1 13 0 1 x x x x x x 0 mmotpvop 0 14 0 1 x x x x x x 0 mmvopcal 4 15 0 1 x x x x x x 0 mmvopcal 3 16 0 1 x x x x x x 0 mmvopcal 2 17 0 1 x x x x x x 0 mmvopcal 1 18 0 1 x x x x x x 0 mmvopcal 0 19 0 1 x x x x x x 0 seal bit; remain in calmm mode 20 apply programming voltage at pins t6 and v lcdin according to section 18.8 repeat steps 6 to 20 for each bit that should be programmed to 1 21 apply external reset
2002 jan 17 34 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 18.8 programming speci?cation table 14 programming speci?cation; see fig.24 notes 1. the voltage drop across the i to track and zebra connector must be taken into account to guarantee sufficient voltage at the chip pins. 2. the maximum voltage must not be exceeded even for a short period of time. therefore care must be taken when applying programming waveforms to avoid overshoot. 3. the power-down mode (don = 0 and dal = 1) and calmm mode must be active while the v lcdin pin is being driven. symbol parameter condition min. typ. max. unit v t6 voltage applied to t6 pin relative to v ss1 programming active; notes 1 and 2 11 11.5 12 v programming inactive; notes 1 and 2 v ss - 0.2 0 0.2 v v lcdin voltage applied to v lcdin pin relative to v ss1 programming active; notes 1 and 3 9 9.5 10 v programming inactive; notes 1 and 3 - 0.2 0 +4.5 v i lcdin current drawn by v lcdin during programming when programming a single bit to logic 1 - 850 1000 m a i t6 current drawn by v t6 during programming - 100 200 m a t amb(prog) ambient temperature during programming 02540 c t su;sclk set-up of internal data after last clock 1 --m s t h;sclk hold of internal data before next clock 1 --m s t su;t6 set-up of v t6 prior to programming 1 - 10 ms t h;t6 hold of v t6 after programming 1 - 10 ms t w pulse width of programming voltage 100 120 200 ms handbook, full pagewidth sclk t sw;sclk t sw;t6 t h;t6 t w mgu291 v t6 v lcdin t h;sclk fig.24 programming waveforms.
2002 jan 17 35 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 19 bonding pad locations table 15 bonding pad information pad rows and cols side interface side unit pad pitch minimum 60 minimum 70 m m pad size (aluminium) 50 90 60 100 m m cbb opening 26 66 36 76 m m bump dimensions 40 80 17.5 ( 5) 50 90 17.5 ( 5) m m wafer thickness (excluding bumps) 381 ( 25) m m handbook, halfpage mgu292 9.46 mm pitch 1.91 mm y x om6211 fig.25 chip size and pad pitch. mgt855 handbook, halfpage x center y center 100 m m fig.26 shape of alignment mark.
2002 jan 17 36 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 table 16 bonding pad location all x and y co-ordinates are referenced to the centre of the chip (dimensions in m m; see fig.27). symbol pad coordinates xy dummy 1 - 835 +4630 alignment mark 2 - 825 +4527.5 v os4 3 - 835 +4425 v os3 4 - 835 +4215 v os2 5 - 835 +4005 v os1 6 - 835 +3795 v os0 7 - 835 +3585 t6 8 - 835 +3375 t6 9 - 835 +3305 t6 10 - 835 +3235 t6 11 - 835 +3165 dummy 12 - 835 +3095 dummy 13 - 835 +3025 dummy 14 - 835 +2955 dummy 15 - 835 +2885 res 16 - 835 +2395 t5 17 - 835 +2185 t4 18 - 835 +1975 t3 19 - 835 +1765 t2 20 - 835 +1555 t1 21 - 835 +1345 sce 22 - 835 +1135 v ss2 23 - 835 +1065 v ss2 24 - 835 +995 v ss2 25 - 835 +925 v ss2 26 - 835 +855 v ss2 27 - 835 +785 v ss2 28 - 835 +715 v ss2 29 - 835 +645 v ss2 30 - 835 +575 v ss1 31 - 835 +505 v ss1 32 - 835 +435 v ss1 33 - 835 +365 v ss1 34 - 835 +295 v ss1 35 - 835 +225 v ss1 36 - 835 +155 v ss1 37 - 835 +85 v ss1 38 - 835 +15 dummy 39 - 835 - 405 osc 40 - 835 - 825 sdout 41 - 835 - 1035 sdin 42 - 835 - 1245 sclk 43 - 835 - 1455 id4 44 - 835 - 1665 id3 45 - 835 - 1875 mx 46 - 835 - 2085 v dd1 47 - 835 - 2155 v dd1 48 - 835 - 2225 v dd1 49 - 835 - 2295 v dd1 50 - 835 - 2365 v dd1 51 - 835 - 2435 v dd1 52 - 835 - 2505 v dd2 53 - 835 - 2575 v dd2 54 - 835 - 2645 v dd2 55 - 835 - 2715 v dd2 56 - 835 - 2785 v dd2 57 - 835 - 2855 v dd2 58 - 835 - 2925 v dd2 59 - 835 - 2995 v dd2 60 - 835 - 3065 v dd3 61 - 835 - 3135 v dd3 62 - 835 - 3205 v dd3 63 - 835 - 3275 v dd3 64 - 835 - 3345 v lcdsense 65 - 835 - 3415 v lcdout 66 - 835 - 3485 v lcdout 67 - 835 - 3555 v lcdout 68 - 835 - 3625 v lcdout 69 - 835 - 3695 v lcdout 70 - 835 - 3765 v lcdout 71 - 835 - 3835 v lcdout 72 - 835 - 3905 v lcdin 73 - 835 - 3975 v lcdin 74 - 835 - 4045 v lcdin 75 - 835 - 4115 v lcdin 76 - 835 - 4185 symbol pad coordinates xy
2002 jan 17 37 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 v lcdin 77 - 835 - 4255 v lcdin 78 - 835 - 4325 dummy 79 - 835 - 4395 alignment mark 80 - 825 - 4500 dummy 81 - 835 - 4605 dummy 82 +840 - 4590 dummy 83 +840 - 4530 dummy 84 +840 - 4470 dummy 85 +840 - 4410 dummy 86 +840 - 4350 dummy 87 +840 - 4290 dummy 88 +840 - 4230 row 0 89 +840 - 4050 row 1 90 +840 - 3990 row 2 91 +840 - 3930 row 3 92 +840 - 3870 row 4 93 +840 - 3810 row 5 94 +840 - 3750 row 6 95 +840 - 3690 row 7 96 +840 - 3630 row 8 97 +840 - 3570 row 9 98 +840 - 3510 row 10 99 +840 - 3450 row 11 100 +840 - 3390 row 12 101 +840 - 3330 row 13 102 +840 - 3270 row 14 103 +840 - 3210 row 15 104 +840 - 3150 row 16 105 +840 - 3090 row 17 106 +840 - 3030 row 18 107 +840 - 2970 row 19 108 +840 - 2910 row 20 109 +840 - 2850 row 21 110 +840 - 2790 row 22 111 +840 - 2730 row 23 112 +840 - 2670 col 0 113 +840 - 2490 col 1 114 +840 - 2430 col 2 115 +840 - 2370 symbol pad coordinates xy col 3 116 +840 - 2310 col 4 117 +840 - 2250 col 5 118 +840 - 2190 col 6 119 +840 - 2130 col 7 120 +840 - 2070 col 8 121 +840 - 2010 col 9 122 +840 - 1950 col 10 123 +840 - 1890 col 11 124 +840 - 1830 col 12 125 +840 - 1770 col 13 126 +840 - 1710 col 14 127 +840 - 1650 col 15 128 +840 - 1590 col 16 129 +840 - 1530 col 17 130 +840 - 1470 col 18 131 +840 - 1410 col 19 132 +840 - 1350 col 20 133 +840 - 1290 col 21 134 +840 - 1230 col 22 135 +840 - 1170 col 23 136 +840 - 1110 col 24 137 +840 - 1050 col 25 138 +840 - 990 col 26 139 +840 - 930 col 27 140 +840 - 870 col 28 141 +840 - 690 col 29 142 +840 - 630 col 30 143 +840 - 570 col 31 144 +840 - 510 col 32 145 +840 - 450 col 33 146 +840 - 390 col 34 147 +840 - 330 col 35 148 +840 - 270 col 36 149 +840 - 210 col 37 150 +840 - 150 col 38 151 +840 - 90 col 39 152 +840 - 30 col 40 153 +840 +30 col 41 154 +840 +90 symbol pad coordinates xy
2002 jan 17 38 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 col 42 155 +840 +150 col 43 156 +840 +210 col 44 157 +840 +270 col 45 158 +840 +330 col 46 159 +840 +390 col 47 160 +840 +450 col 48 161 +840 +510 col 49 162 +840 +570 col 50 163 +840 +630 col 51 164 +840 +690 col 52 165 +840 +750 col 53 166 +840 +810 col 54 167 +840 +870 col 55 168 +840 +930 col 56 169 +840 +1110 col 57 170 +840 +1170 col 58 171 +840 +1230 col 59 172 +840 +1290 col 60 173 +840 +1350 col 61 174 +840 +1410 col 62 175 +840 +1470 col 63 176 +840 +1530 col 64 177 +840 +1590 col 65 178 +840 +1650 col 66 179 +840 +1710 col 67 180 +840 +1770 col 68 181 +840 +1830 col 69 182 +840 +1890 col 70 183 +840 +1950 col 71 184 +840 +2010 col 72 185 +840 +2070 col 73 186 +840 +2130 col 74 187 +840 +2190 col 75 188 +840 +2250 col 76 189 +840 +2310 col 77 190 +840 +2370 col 78 191 +840 +2430 col 79 192 +840 +2490 col 80 193 +840 +2550 symbol pad coordinates xy col 81 194 +840 +2610 col 82 195 +840 +2670 col 83 196 +840 +2730 row 47 197 +840 +2910 row 46 198 +840 +2970 row 45 199 +840 +3030 row 44 200 +840 +3090 row 43 201 +840 +3150 row 42 202 +840 +3210 row 41 203 +840 +3270 row 40 204 +840 +3330 row 39 205 +840 +3390 row 38 206 +840 +3450 row 37 207 +840 +3510 row 36 208 +840 +3570 row 35 209 +840 +3630 row 34 210 +840 +3690 row 33 211 +840 +3750 row 32 212 +840 +3810 row 31 213 +840 +3870 row 30 214 +840 +3930 row 29 215 +840 +3990 row 28 216 +840 +4050 row 27 217 +840 +4110 row 26 218 +840 +4170 row 25 219 +840 +4230 row 24 220 +840 +4290 dummy 221 +840 +4350 dummy 222 +840 +4410 dummy 223 +840 +4470 dummy 224 +840 +4530 dummy 225 +840 +4590 symbol pad coordinates xy
2002 jan 17 39 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 mgu293 dummy pad dummy pad dummy pad col 0 row 0 dummy pad dummy pad dummy pad t6 alignment mark alignment mark om6211-1 v os3 v os2 v os4 v os1 v os0 . . . row 23 . . . col 27 . . . . . . col 28 col 55 . . . . . . col 56 col 83 . . . . . . row 24 row 47 . . . . . . v ss1 v ss2 v lcdsense v lcdout v dd1 v dd2 v dd3 osc dummy pad sce res t5 t4 t3 t2 t1 sdout sdin id3 id4 sclk mx v lcdin x y 0, 0 fig.27 pad locations.
2002 jan 17 40 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 20 device protection diagram handbook, full pagewidth mgu294 v dd1 v dd1 v ss1 v ss2 v ss1 v os [4:0] v ss1 v ss1 v dd1 osc, sdin, sclk, sce, res, t4, t5, mx, id3, id4 v lcdout v ss1 v lcdin (supply), v lcdsense v lcdin v ss1 v dd2 v ss1 v ss2 v dd1 v ss1 v ss1 t6 v dd3 v ss1 v lcdin v ss1 sdout, t1, t2, t3 col0 to col83 row0 to row47 fig.28 device protection diagram. the conditions for continuity tests are as follows: maximum forward current = 5 ma; maximum reverse voltage = 5 v.
2002 jan 17 41 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 21 tray information handbook, full pagewidth mgu295 d f e x y a 1,1 x,1 2,1 1,2 1,3 1,y x,y 2,2 3,1 c b fig.29 tray details. table 17 tray dimensions handbook, halfpage om6211-1 mgu296 fig.30 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to the bonding pad location diagram for the orientation and position of the type name on the surface. dimension description value a pocket pitch x direction 13.76 mm b pocket pitch y direction 4.45 mm c pocket width x direction 9.56 mm d pocket width y direction 2.00 mm e tray width x direction 50.80 mm f tray width y direction 50.80 mm x number of pockets in x direction 3 y number of pockets in y direction 10
2002 jan 17 42 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 22 application notes when reading the vm bit in the om6211 two problems have been observed: corrupted format and vm bit toggling. 22.1 corrupted format the read-out of the vm bit has a special format, 11110000 for vm = 1 and 00001111 for vm = 0. however, sometimes a wrong format of the read-out byte can be observed; the first or the fifth or the eighth bit appears to be wrong. there are two reasons for this behaviour. when the first bit happens to be read out at the end of a frame then it is possible that the first bit belongs to the old vm value and the 7 following bits belong to the new vm value. such behaviour is possible for the first bit only. the second reason is the violation of the om6211 timing, if the timing parameters t 2 and t 3 (see fig.17) are violated, then it results in reading a wrong value for the first, the fifth or the eighth bit. thus, to prevent any problems with the wrong format of the read-out byte, these bits should always be ignored. 22.2 vm bit toggling under certain conditions it can happen that the result of reading vm is 0 even if the generated v lcd voltage is correct (vm bit toggles). it is therefore recommended to repeat the vm read command several times according to the algorithm described below. this algorithm is based on the observation that a single reading of vm = 1 (after numerous readings of vm = 0) is enough to ensure that the charge pump operation is correct. one possible method which gives minimum measurement duration is shown in fig.31 and described in detail below: perform initialization with enable otp and set the operational parameters (v pr = 159, s = 10, bs = 101, tc = 1, e = 0 and my = 0) this results in a slightly higher v lcd voltage than for normal operation (v lcd = 8.732 v at t amb =27 c) select dal = 1 and don = 1 (for all pixels on) after setting hve = 1 start a loop of a continuous vm reading (for example, every 1 ms), at first occurrence of reading vm = 1 interrupt the loop and accept vm = 1 when the reading is always vm = 0, stop the loop after a certain time and accept vm = 0. this loop time limit should be chosen sufficiently long, e.g. 85 ms. given that the uncertainty is much less then 0.1%, much less then 1 ppm is expected to be read out wrong. for the loop time limit a value of not less than 85 ms is suggested. it should be noted that the value of 45 ms specified in section 11.2.2 means that after at least 45 ms the vm measurement is possible. in practice it can be expected that vm is valid earlier than 45 ms. therefore the proposed algorithm results in an optimization of the 45 ms wait time needed to charge the external v lcd capacitor. so the selected loop time limit of 85 ms consists of 45 ms wait time and an additional 40 ms of measurement time. the loop time limit of 85 ms will ensure that even if the first vm = 1 value for any reason should be missed, there is always the possibility to hit the next vm = 1 value (note that the internal vm measurement is made once per 12.5 ms). however, the expectation is that the average running time of the loop will be less than 45 ms . there is another possibility for optimization: during the wait time of the loop (1 ms) other tasks can be performed. furthermore the first part of the 45 ms wait time, just after setting hve = 1, may also be used for other tasks. for instance when the first 20 ms are reserved for those tasks, then the corresponding loop time limit would be 65 ms and the expected average loop time would be less than 25 ms. after the vm test is completed the v pr can be set to the desired value (e.g. v pr = 137) without the charge pump being switched off.
2002 jan 17 43 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 handbook, halfpage initialization hve = 1 loop_time_limit = 85 ms reset time_counter read vm bit yes yes wait 1 ms no no vm = 1 ? end mgu521 time_counter < loop_time_limit? fig.31 algorithm of reliable and fast read-out of the vm bit.
2002 jan 17 44 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 23 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 24 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 25 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 jan 17 45 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 notes
2002 jan 17 46 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 notes
2002 jan 17 47 philips semiconductors product speci?cation 48 84 dot matrix lcd driver om6211 notes
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 403512/01/pp 48 date of release: 2002 jan 17 document order number: 9397 750 07744

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